ARM Cortex A9 CPU subsystem

Processor subsystem based on the processor ARM Cortex A9, and has a dual-core configuration.

Key Features:

Each core has the following features:

ARM v7 processor with a clock frequency of 600 MHz
32K L1 Instruction Cache parity
32 KB L1 data cache parity
Built-in FPU operations for single and double precision data scalar floating-point
The memory management unit (MMU)
Instruction set support for ARM, Thumb2 and Thumb2-EE
Program Trace Macrocell (PTM) and CoreSight © component for software debugging
32-bit timer with 8-bit divisor
The internal watchdog (also works as a timer)

Dual core configuration completes a common set of components:

Snoop Control Unit (SCU) for controlling communication between processes, cache memory and cache memory and transfer RAM, cache coherency
Shared interrupt control unit (GCA) is configured to support 128 independent interrupt sources with software configurable priorities and routing between the two nuclei
64-bit global timer with an 8-bit divisor
Accelerator coherence port (ACP)
Support for parity for fault detection performance for other internal memories
512 KB single 8-way associative L2 cache with ECC support
L2 cache controller based on ARM PL310 IP released
Dual asynchronous 64-bit AMBA 3 AXI interface with the ability to filter on the second use one port to access DDR memory
JTAG-interface and monitor port: debug and trace may be prohibited by OTP

Comments

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